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functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a loop-powered 4C20 ma sensor transmitter one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 AD693 features instrumentation amplifier front end loop-powered operation precalibrated 30 mv or 60 mv input spans independently adjustable output span and zero precalibrated output spans: 4C20 ma unipolar 0C20 ma unipolar 12 6 8 ma bipolar precalibrated 100 v rtd interface 6.2 v reference with up to 3.5 ma of current available uncommitted auxiliary amp for extra flexibility optional external pass transistor to reduce self-heating errors product description the AD693 is a monolithic signal conditioning circuit which accepts low-level inputs from a variety of transducers to control a standard 4C20 ma, two-wire current loop. an on-chip voltage reference and auxiliary amplifier are provided for transducer excitation; up to 3.5 ma of excitation current is available when the device is operated in the loop-powered mode. alternatively, the device may be locally powered for three-wire applications when 0C20 ma operation is desired. precalibrated 30 mv and 60 mv input spans may be set by simple pin strapping. other spans from 1 mv to 100 mv may be realized with the addition of external resistors. the auxiliary amplifier may be used in combination with on-chip voltages to provide six precalibrated ranges for 100 w rtds. output span and zero are also determined by pin strapping to obtain the standard ranges: 4C20ma, 12 8 ma and 0C20 ma. active laser trimming of the AD693s thin-film resistors result in high levels of accuracy without the need for additional adjustments and calibration. total unadjusted error is tested on every device to be less than 0.5% of full scale at +25 c, and less than 0.75% over the industrial temperature range. residual nonlinearity is under 0.05%. the AD693 also allows for the use of an external pass transistor to further reduce errors caused by self-heating. for transmission of low-level signals from rtds, bridges and pressure transducers, the AD693 offers a cost-effective signal conditioning solution. it is recommended as a replacement for discrete designs in a variety of applications in process control, factory automation and system monitoring. the AD693 is packaged in a 20-pin ceramic side-brazed dip, 20-pin cerdip, and 20-pin lccc and is specified over the C40 c to +85 c industrial temperature range. product highlights 1. the AD693 is a complete monolithic low-level voltage-to- current loop signal conditioner. 2. precalibrated output zero and span options include 4C20 ma, 0C20 ma, and 12 8 ma in two- and three-wire configurations. 3. simple resistor programming adds a continuum of ranges to the basic 30 mv and 60 mv input spans. 4. the common-mode range of the signal amplifier input extends from ground to near the devices operating voltage. 5. provision for transducer excitation includes a 6.2 v reference output and an auxiliary amplifier which may be configured for voltage or current output and signal amplification. 6. the circuit configuration permits simple linearization of bridge, rtd, and other transducer signals. 7. a monitored output is provided to drive an external pass transistor. this feature off-loads power dissipation to extend the temperature range of operation, enhance reliability, and minimize self-heating errors. 8. laser-wafer trimming results in low unadjusted errors and affords precalibrated input and output spans. 9. zero and span are independently adjustable and noninteractive to accommodate transducers or user defined ranges. 10. six precalibrated temperature ranges are available with a 100 w rtd via pin strapping.
AD693Cspecifications rev. a C2C (@ +25 8 c and v s = +24 v. input span = 30 mv or 60 mv. output span = 4C20 ma, r l = 250 v , v cm = 3.1 v, with external pass transistor unless otherwise noted.) model AD693ad/aq/ae conditions min typ max units loop-powered operation total unadjusted error 1, 2 0.25 6 0.5 % full scale t min to t max 0.4 6 0.75 % full scale 100 w rtd calibration error 3 (see figure 17) 0.5 2.0 c loop powered operation 2 zero current error 4 zero = 4 ma 25 6 80 m a zero = 12 ma 40 6 120 m a zero = 0 ma 5 +7 +35 +100 m a vs. temp. zero = 4 ma 0.5 1.5 m a/ c power supply rejection (rti) 12 v v op 36v 6 3.0 6 5.6 m v/v 0 v v cm 6.2 v common-mode input range (see figure 3) 0 +v op C 4 v 6 v common-mode rejection (rti) 0 v v cm 6.2 v 10 6 30 m v/v input bias current 7 +5 +20 na t min to t max +7 +25 na input offset current 7 v sig = 0 0.5 6 3.0 na transconductance nominal 30 mv input span 0.5333 a/v 60 mv input span 0.2666 a/v unadjusted error 0.05 6 0.2 % vs. common-mode 0 v v cm 6.2 v 30 mv input span 0.03 0.04 %/v 60 mv input span 0.05 0.06 %/v error vs. temp. 20 50 ppm/ c nonlinearity 8 30 mv input span 0.01 6 0.05 % of span 60 mv input span 0.02 6 0.07 % of span operational voltage range operational voltage, v op 6 +12 +36 v quiescent current into pin 9 +500 +700 m a output current limit +21 +25 +32 ma components of error signal amplifier 9 input voltage offset 40 6 200 m v vs. temp 1.0 2.5 m v/ c power supply rejection 12 v v op 36 v 6 3.0 6 5.6 m v/v 0 v v cm 6.2 v v/i converter 9, 10 zero current error output span = 4C20 ma 30 80 m a power supply rejection 12 v v op 36 v 6 1.0 3.0 m a/v transconductance nominal 0.2666 a/v unadjusted error 0.05 0.2 % 6.200 v reference 9, 12 output voltage tolerance 3 6 12 mv vs. temp. 20 50 ppm/ c line regulation 12 v v op 36 v 6 200 6 300 m v/v load regulation 11 0 ma i ref 3 ma 0.3 6 0.75 mv/ma output current 13 loop powered, (figure 10) +3.0 +3.5 ma 3-wire mode, (figure 15) +5.0 ma
model AD693ad conditions min typ max units auxiliary amplifier common-mode range 0 +v op C 4 v 6 v input offset voltage 50 200 m v input bias current +5 +20 na input offset current +0.5 3.0 na common-mode rejection 90 db power supply rejection 105 db output current range pin i x out +0.01 +5 ma output current error pin v x C pin i x 0.005 % temperature range case operating 14 t min to t max C40 +85 c storage C65 +150 c notes 1 total error can be significantly reduced (typically less than 0.1%) by trimming the zero current. the remaining unadjusted error sources are transconductance and nonlinearity. 2 the AD693 is tested as a loop powered device with the signal amp, v/i converter, voltage reference, and application voltages operating together. specifications are valid for preset spans and spans between 30 mv and 60 mv. 3 error from ideal output assuming a perfect 100 w rtd at 0 and +100 c. 4 refer to the error analysis to calculate zero current error for input spans less than 30 mv. 5 by forcing the differential signal amplifier input sufficiently negative the 7 m a zero current can always be achieved. 6 the operational voltage (v op ) is the voltage directly across the AD693 (pin 10 to 6 in two-wire mode, pin 9 to 6 in local power mode). for example, v op = v s C (i loop r l ) in two-wire mode (refer to figure 10). 7 bias currents are not symmetrical with input signal level and flow out of the input pins. the input bias current of the inverting input increases with input signal volt- age, see figure 2. 8 nonlinearity is defined as the deviation of the output from a straight line connecting the endpoints as the input is swept over a 30 mv and 60 mv input span. 9 specifications for the individual functional blocks are components of error that contribute to, and that are included in, the loop powered operation specifications. 10 includes error contributions of v/i converter and application voltages. 11 changes in the reference output voltage due to load will affect the zero current. a 1% change in the voltage reference output will result in an error of 1% in the value of the zero current. 12 if not used for external excitation, the reference should be loaded by approximately 1 ma (6.2 k w to common). 13 in the loop powered mode up to 5 ma can be drawn from the reference, however, the lower limit of the output span will be increased accordingly. 3.5 ma is the maximum current the reference can source while still maintaining a 4 ma zero. 14 the AD693 is tested with a pass transistor so t a @ t c . specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 v reverse loop current . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma signal amp input range . . . . . . . . . . . . . . . . . . C0.3 v to v op reference short circuit to common . . . . . . . . . . . . indefinite auxiliary amp input voltage range . . . . . . . . . . 0.3 v to v op auxiliary amp current output . . . . . . . . . . . . . . . . . . . 10 ma storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature, 10 sec soldering . . . . . . . . . . . . . +300 c max junction temperature . . . . . . . . . . . . . . . . . . . . . +150 c ordering guide package package model description option AD693ad ceramic side-brazed dip d-20 AD693aq cerdip q-20 AD693ae leadless ceramic chip e-20a carrier (lccc) AD693 pin configuration (ad, aq, ae packages) functional diagram C3C rev. a AD693
figure 1. maximum load resistance vs. power supply figure 2. differential input current vs. input signal voltage normalized to +in figure 3. maximum common-mode voltage vs. supply AD693Ctypical characteristics rev. a C4C figure 4. bandwidth vs. series load resistance figure 5. signal amplifier psrr vs. frequency figure 6. cmrr (rti) vs. frequency figure 7. input current noise vs. frequency figure 8. input voltage noise vs. frequency
AD693 rev. a C5C converters inverting input (pin 12). arranging the zero offset in this way makes the zero signal output current independent of input span. when the input to the signal amp is zero, the noninverting input of the v/i is at 6.2 v. since the standard offsets are laser trimmed at the factory, adjustment is seldom necessary except to accommodate the zero offset of the actual source. (see adjusting zero.) signal amplifier the signal amplifier is an instrumentation amplifier used to buffer and scale the input to match the desired span. inputs applied to the signal amplifier (at pins 17 and 18) are amplified and referred to the 6.2 v reference output in much the same way as the level translation occurs in the v/i converter. signals from the two preamplifiers are subtracted, the difference is amplified, and the result is fed back to the upper preamp to minimize the difference. since the two preamps are identical, this minimum will occur when the voltage at the upper preamp just matches the differential input applied to the signal amplifier at the left. since the signal which is applied to the v/i is attenuated across the two 800 w resistors before driving the upper preamp, it will necessarily be an amplified version of the signal applied between pins 17 and 18. by changing this attenuation, you can control the span referred to the signal amplifier. to illustrate: a 75 mv signal applied to the v/i results in a 20 ma loop current. nominally, 15 mv is applied to offset the zero to 4 ma leaving a 60 mv range to correspond to the span. and, since the nominal attenuation of the resistors connected to pins 16, 15 and 14 is 2.00, a 30 mv input signal will be doubled to result in 20 ma of loop current. shorting pins 15 and 16 results in unity gain and permits a 60 mv input span. other choices of span may be implemented with user supplied resistors to modify the attenuation. (see section adjusting input span.) the signal amplifier is specially designed to accommodate a large common-mode range. common-mode signals anywhere up to and beyond the 6.2 v reference are easily handled as long as v in is sufficiently positive. the signal amplifier is biased with respect to v in and requires about 3.5 volts of headroom. the extended range will be useful when measuring sensors driven, for example, by the auxiliary amplifier which may go above the 6.2 v potential. in addition, the pnp input stage will continue to operate normally with common-mode voltages of several hundred mv, negative, with respect to common. this feature accommodates self-generating sensors, such as thermocouples, which may produce small negative normal-mode signals as well as common-mode noise on grounded signal sources. auxiliary amplifier the auxiliary amplifier is included in the AD693 as a signal conditioning aid. it can be used as an op amp in noninverting applications and has special provisions to provide a controlled current output. designed with a differential input stage and an unbiased class a output stage, the amplifier can be resistively loaded to common with the self-contained 100 w resistor or with a user supplied resistor. as a functional element, the auxiliary amplifier can be used in dynamic bridges and arrangements such as the rtd signal conditioner shown in figure 17. it can be used to buffer, amplify and combine other signals with the main signal amplifier. the auxiliary amplifier can also provide other voltages for excitation functional description the operation of the AD693 can be understood by dividing the circuit into three functional parts (see figure 9). first, an instrumentation amplifier front-end buffers and scales the low- level input signal. this amplifier drives the second section, a v/i converter, which provides the 4-to-20ma loop current. the third section, a voltage reference and resistance divider, provides application voltages for setting the various live zero currents. in addition to these three main sections, there is an on-chip auxiliary amplifier which can be used for transducer excitation. voltage-to-current (v/i) converter the output npn transistor for the v/i section sinks loop current when driven on by a high gain amplifier at its base. the input for this amplifier is derived from the difference in the outputs of the matched preamplifiers having gains, g2. this difference is caused to be small by the large gain, +a, and the negative feedback through the npn transistor and the loop current sampling resistor between i in and boost. the signal across this resistor is compared to the input of the left preamp and servos the loop current until both signals are equal. accurate voltage-to-current transformation is thereby assured. the preamplifiers employ a special design which allows the active feedback amplifier to operate from the most positive point in the circuit, i in. the v/i stage is designed to have a nominal transconductance of 0.2666 a/v. thus, a 75 mv signal applied to the inputs of the v/i (pin 16, noninverting; pin 12, inverting) results in a full-scale output current of 20 ma. the current limiter operates as follows: the output of the feed- back preamp is an accurate indication of the loop current. this output is compared to an internal setpoint which backs off the drive to the npn transistor when the loop current approaches 25 ma. as a result, the loop and the AD693 are protected from the consequences of voltage overdrive at the v/i input. voltage reference and divider a stabilized bandgap voltage reference and laser-trimmed resistor divider provide for both transducer excitation as well as precalibrated offsets for the v/i converter. when not used for external excitation, the reference should be loaded by approxi- mately 1 ma (6.2 k w to common). the 4 ma and 12 ma taps on the resistor divider correspond to C15 mv and C45 mv, respectively, and result in a live zero of 4 ma or 12 ma of loop current when connected to the v/i figure 9. functional flock diagram
AD693 rev. a C6C if the 6.2 v of the reference is unsuitable. configured as a simple follower, it can be driven from a user supplied voltage divider or the precalibrated outputs of the AD693 divider (pins 3 and 4) to provide a stiff voltage output at less than the 6.2 level, or by incorporating a voltage divider as feedback around the amplifier, one can gain-up the reference to levels higher than 6.2 v. if large positive outputs are desired, i x , the auxiliary amplifier output current supply, should be strapped to either v in or boost. like the signal amplifier, the auxiliary requires about 3.5 v of headroom with respect to v in at its input and about 2 v of difference between i x and the voltage to which v x is required to swing. the output stage of the auxiliary amplifier is actually a high gain darlington transistor where i x is the collector and v x is the emitter. thus, the auxiliary amplifier can be used as a v/i converter when configured as a follower and resistively loaded. i x functions as a high-impedance current source whose current is equal to the voltage at v x divided by the load resistance. for example, using the onboard 100 w resistor and the 75 mv or 150 mv application voltages, either a 750 m a or 1.5 ma current source can be set up for transducer excitation. the i x terminal has voltage compliance within 2 v of v x . if the auxiliary amplifier is not to be used, then pin 2, the noninverting input, should be grounded. reverse voltage protection feature in the event of a reverse voltage being applied to the AD693 through a current-limited loop (limited to 200 ma), an internal shunt diode protects the device from damage. this protection mode avoids the compliance voltage penalty which results from a series diode that must be added if reversal protection is required in high-current loops. applying the AD693 connections for basic operation figure 10 shows the minimal connections for basic operation: 0C30 mv input span, 4C20 ma output span in the two-wire, loop-powered mode. if not used for external excitation, the 6.2 v reference should be loaded by approximately 1 ma (6.2 k w to common). using an external pass transistor the emitter of the npn output section, i out , of the AD693 is usually connected to common and the negative loop connection (pins 7 to 6). provision has been made to reconnect i out to the base of a user supplied npn transistor as shown in figure 11. this permits the majority of the power dissipation to be moved off chip to enhance performance, improve reliability, and extend the operating temperature range. an internal hold-down resistor of about 3k is connected across the base emitter of the external transistor. the external pass transistor selected should have a bv ceo greater than the intended supply voltage with a sufficient power rating for continuous operation with 25 ma current at the supply voltage. ft should be in the 10 mhz to 100 mhz range and b should be greater than 10 at a 20 ma emitter current. some transistors that meet this criteria are the 2n1711 and 2n2219a. heat sinking the external pass transistor is suggested. the pass transistor option may also be employed for other applications as well. for example, i out can be used to drive an led connected to common, thus providing a local monitor of loop fault conditions without reducing the minimum compliance voltage. adjusting zero in general, the desired zero offset value is obtained by connecting an appropriate tap of the precision reference/voltage divider network to the inverting terminal of the v/i converter. as shown in figure 9, precalibrated taps at pins 14, 13 and 11 result in zero offsets of 0 ma, 4 ma and 12 ma, respectively, when connected to pin 12. the voltages which set the 4 ma and 12 ma zero operating points are 15 mv and 45 mv negative with respect to 6.2 v, and they each have a nominal source resistance of 450 w . while these voltages are laser trimmed to high accuracy, they may require some adjustment to accommodate variability between sensors or to provide additional ranges. you can adjust zero by pulling up or down on the selected zero tap, or by making a separate voltage divider to drive the zero pin. the arrangement of figure 12 will give an approximately linear adjustment of the precalibrated options with fixed limits. to find the proper resistor values, first select i a , the desired range figure 10. minimal connection for 0C30 mv unipolar input, 4C20 ma output
AD693 rev. a C7C figure 11. using an external pass transistor to minimize self-heating errors of adjustment of the output current from nominal. substitute this value in the appropriate formula below for adjustment at the 4 ma tap. r z 1 = (1.6 v/i a ) C 400 w and r z 2 = r z1 3.1 v /(15 mv + i a 3.75 w ) use a similar connection with the following resistances for adjustments at the 12 ma tap. r z1 = (4.8 v/i a ) C 400 w and r z2 = r z 1 3.1 v /(45 mv + i a 3.75 w ) these formulae take into account the 10% tolerance of tap resistance and insure a minimum adjustment range of i a . for example, choosing i a = 200 m a will give a zero adjustment range of 1% of the 20 ma full-scale output. at the 4 ma tap the maximum value of: r z1 = 1.6 v/200 m a C 400 w = 7.6 k w and r z2 = 7.6 k w 3.1 v/(15 mv + 200 m a 3.75 w ) = 1.49 m w figure 12. optional 4 ma zero adjustment (12 ma trim available also) these can be rounded down to more convenient values of 7.5 k w and 1.3 m w , which will result in an adjustment range comfortably greater than 200 m a. adjusting input span input span is adjusted by changing the gain of the signal amplifier. this amplifier provides a 0-to-60 mv signal to the v/i section to produce the 4-to-20 ma output span (or a 0-to-75 mv signal in the 0-to-20 ma m ode). the gain of this amplifier is trimmed to 2.00 so that an input signal ranging from 0-to-30 mv will drive the v/i section to produce 4-to -20 ma. joining p1 and p2 (pins 15 and 16) will reduce the signal ampli- fier gain to one, thereby requiring a 60 mv signal to drive the v/i to a full 20 ma span. to produce spans less than 30 mv, an external resistor, r s1 , can be connected between p1 and 6.2 v. the nominal value is given by: r s 1 = 400 w 30 mv s - 1 where s is the desired span. for example, to change the span to 6 mv a value of: r s 1 = 400 w 30 mv 6 mv - 1 = 100 w is required. since the internal, 800 w gain setting resistors exhibit an absolute tolerance of 10%, r s1 should be provided with up to 10% range of adjustment if the span must be well controlled. for spans between 30 mv and 60 mv a resistor r s2 should be connected between p1 and p2. the nominal value is given by: r s 2 = 400 w 1 - 60 mv s ? ? ? ? 30 mv s - 1 for example, to change the span to 40 mv, a value of: r s 2 = 400 w 1 - 60 mv 40 mv ? ? ? ? 30 mv 40 mv - 1 = 800 w is required. remember that this is a nominal value and may require adjustment up to 10%. in many applications the span must be adjusted to accommodate individual variations in the sensor as well as the AD693. the span changing resistor should, therefore, include enough adjustment range to handle both the sensor uncertainty and the absolute resistance tolerance of p1 and p2. note that the temperature coefficient of the internal resistors is nominally C17 ppm/ c, and that the external resistors should be comparably stable to insure good tempera- ture performance.
AD693 rev. a C8C r e 2 = r d s s - 60 mv - 1.0024 ? ? ? ? and r e 1 = 412 r e 2 figure 14 shows a scheme for adjusting the modified span and 4 ma offset via r e3 and r e4 . the trim procedure is to first connect both signal inputs to the 6.2 v reference, set r e4 to zero and then adjust r e3 so that 4 ma flows in the current loop. this in effect, creates a divider with the same ratio as the internal divider that sets the 4 ma zero level (C15 mv with respect to 6.2 v). as long as the input signal remains zero the voltage at pin 12, the zero adjust, will remain at C15 mv with respect to 6.2 v. figure 14. adjusting for spans between 60 mv and 100 mv (r e1 and r e2 ) with fine-scale adjust (r e3 and r e4 ) after adjusting r e3 place the desired full scale (s) across the signal inputs and adjust r e4 so that 20 ma flows in the current loop. an attenuated portion of the input signal is now added into the v/i zero to maintain the 75 mv maximum differential. if there is some small offset at the input to the signal amplifier, it may be necessary to repeat the two adjustments. local-powered operation for 0C20 ma output the AD693 is designed for local-powered, three-wire systems as well as two-wire loops. all its usual ranges are available in three- wire operation, and in addition, the 0C20 ma range can be used. the 0-20 ma convention offers slightly more resolution and may simplify the loop receiver, two reasons why it is sometimes preferred. the arrangement, illustrated in figure 15, results in a 0C20 ma transmitter where the precalibrated span is 37.5 mv. con- necting p1 to p2 will double the span to 75 mv. sensor input and excitation is unchanged from the two-wire mode except for the 25% increase in span. many sensors are ratiometric so that an increase in excitation can be used instead of a span adjustment. in the local-powered mode, increases in excitation are made easier. voltage compliance at the i in terminal is also improved; the loop voltage may be permitted to fall to 6 volts at the AD693, easing the trade-off between loop voltage and loop resistance. note that the load resistor, r l , should meter the current into pin 10, i in , so as not to confuse the loop current with the local power supply current. an alternative arrangement, allowing wide range span adjust- ment between two set ranges, is shown in figure 13. r s1 and r s2 are calculated to be 90% of the values determined from the previous formulae. the smallest value is then placed in series with the wiper of the 1.5 k w potentiometer shown in the figure. for example, to adjust the span between 25 mv and 40 mv, r s1 and r s2 are calculated to be 2000 w and 800 w , respectively. the smaller value, 800 w , is then reduced by 10% to cover the possible ranges of resistance in the AD693 and that value is put in place. figure 13. wide range span adjustment a number of other arrangements can be used to set the span as long as they are compatible with the pretrimmed noninverting gain of two. the span adjustment can even include thermistors or other sensitive elements to compensate the span of a sensor. in devising your own adjustment scheme, remember that you should adjust the gain such that the desired span voltage at the signal amplifier input translates to 60 mv at the output. note also that the full differential voltage applied to the v/i converter is 75 mv; in the 4-20 ma mode, C15 mv is applied to the inverting input (zero pin) by the divider network and +60 mv is applied to the noninverting input by the signal amplifier. in the 0C20 ma mode, the total 75 mv must be applied by the signal amplifier. as a result, the total span voltage will be 25% larger than that calculated for a 4-20 ma output. finally, the external resistance from p2 to 6.2 v should not be made less than 1 k w unless the voltage reference is loaded to at least 1.0 ma. (a simple load resistor can be used to meet this requirement if a low value potentiometer is desired.) in no case should the resistance from p2 to 6.2 v be less than 200 w . input spans between 60 mv and 100 mv input spans of up to 100 mv can be obtained by adding an offset proportional to the output signal into the zero pin of the v/i converter. this can be accomplished with two resistors and adjusted via the optional trim scheme shown in figure 14. the resistor divider formed by r e1 and r e2 from the output of the signal amplifier modifies the differential input voltage range applied to the v/i converter. in order to determine the fixed resistor values, r e1 and r e2 , first measure the source resistance (r d ) of the internal divider network. this can be accomplished (power supply disconnected) by measuring the resistance between the 4 ma of offset (pin 13) and common (pin 6) with the 6.2 v reference (pin 14) connected to common. the measured value, r d , is then used to calculate r e1 and r e2 via the following formula:
AD693 rev. a C9C figure 15. local powered operation with 0C20 ma output optional input filtering input filtering is recommended for all applications of the AD693 due to its low input signal range. an rc filter network at each input of the signal amplifier is sufficient, as shown in figure 16. in the case of a resistive signal source it may be necessary only to add the capacitors, as shown in figure 18. the capacitors should be placed as close to the AD693 as possible. the value of the filter resistors should be kept low to minimize errors due to input bias current. choose the 3 db point of the filter high enough so as not to compromise the bandwidth of the desired signal. the rc time constant of the filter should be matched to preserve the ac common-mode rejection. figure 16. optional input filtering interfacing platinum rtds the AD693 has been specially configured to accept inputs from 100 w platinum rtds (resistance temperature detectors). referring to figure 17, the rtd and the temperature stable 100 w resistor form a feedback network around the auxiliary amplifier resulting in a noninverting gain of (1 + r t /100 w ), where r t is the temperature dependent resistance of the rtd. the noninverting input of the auxiliary amplifier (pin 2) is then driven by the 75 mv signal from the voltage divider (pin 4). when the rtd is at 0, its 100 w resistance results in an amplifier gain of +2 causing v x to be 150 mv. the signal amplifier compares this voltage to the 150 mv output (pin 3) so that zero differential signal results. as the temperature (and therefore, the resistance) of the rtd increases, v x will likewise increase according to the gain relationship. the difference between this voltage and the zero degree value of 150 mv drives the signal amp to modulate the loop current. the AD693 is precalibrated such that the full 4-20ma output span corresponds to a 0 to 104 c range in the rtd. (this assumes the european standard of a = 0.00385.) a total of 6 precalibrated ranges for three-wire (or two-wire) rtds are available using only the pin strapping options as shown in table i. a variety of other temperature ranges can be realized by using different application voltages. for example, loading the voltage divider with a 1.5 k w resistor from pin 3 to pin 6 (common) will approximately halve the original application voltages and allow for a doubling of the range of resistance (and therefore, temperature) required to fill the two standard spans. likewise, table i. precalibrated temperature range options using a european standard 100 w rtd and the AD693 temperature range pin connections 0 to + 104 c 12 to 13 0 to +211 c 12 to 13, and 15 to 16 +25 c to +130 c 12 to 14 +51 c to +266 c 12 to 14, and 15 to 16 C50 c to +51 c 12 to 11 C100 c to +104 c 12 to 11 and 15 to 16 figure 17. 0-to-104 c direct three-wire 100 w rtd lnterface, 4-20ma output
AD693 rev. a C10C increasing the application voltages by adding resistance between pins 14 and 3 will decrease the temperature span. an external voltage divider may also be used in conjunction with the circuit shown to produce any range of temperature spans as well as providing zero output (4 ma) for a non 0 temperature input. for example, measuring v x with respect to a voltage 2.385 times the excitation (rather than 2 times) will result in zero input to the signal amplifier when the rtd is at 100 c (or 138.5 w ). as suggested in table i, the temperature span may also be adjusted by changing the voltage span of the signal amplifier. changing the gain from 2 to 4, for example, will halve the temperature span to about 52 c on the 4-20ma output configuration. (see section adjusting input span.) the configuration for a three-wire rtd shown in figure 17 can accommodate two-wire sensors by simply joining pins 1 and 5 of the AD693. interfacing load cells and metal foil strain gages the availability of the on-chip voltage reference, auxiliary amplifier and 3 ma of excitation current make it easy to adapt the AD693 to a variety of load cells and strain gages. the circuit shown in figure 18 illustrates a generalized approach in which the full flexibility of the AD693 is required to interface to a low resistance bridge. for a high impedance transducer the bridge can be directly powered from the 6.2 v reference. component values in this example have been selected to match the popular standard of 2 mv/v sensitivity and 350 w bridge resistance. load cells are generally made for either tension and compression, or compression only; use of the 12 ma zero tap allows for operation in the tension and compression mode. an optional zero adjustment is provided with values selected for +2% fs adjustment range. because of the low resistance of most foil bridges, the excitation voltage must be low so as not to exceed the available 4 ma zero current. about 1 v is derived from the 6.2 v reference and an external voltage divider; the aux-amp is then used as a follower to make a stiff drive for the bridge. similar applications with higher resistance sensors can use proportionally higher voltage. finally, to accommodate the 2 mv/v sensitivity of the bridge, the full-scale span of the signal amplifier must be reduced. using the load cell in both tension and compression with 1 v of excitation, therefore, dictates that the span be adjusted to 4 mv. by substituting in the expression, r s1 = 400 w /[(30 mv/s) C 1], the nominal resistance required to achieve this span is found to be 61.54 w . calculate the minimum resistance required by subtracting 10% from 61.54 w to allow for the internal resistor tolerance of the AD693, leaving 55.38 w (see adjusting input span.) the standard value of 54.9 w is used with a 20 w potentiometer for full-scale adjustment. if a load cell with a precalibrated sensitivity constant is to be used, the resultant full-scale span applied to the signal amplifier is found by multiplying that sensitivity by the excitation voltage. (in figure 18, the excitation voltage is actually (10 k w /62.3 k w ) (6.2 v) = 0.995 v). thermocouple measurements the AD693 can be used with several types of thermocouple inputs to provide a 4-20 ma current loop output corresponding to a variety of measurement temperature ranges. cold junction compensation (cjc) can be implemented using an ad592 or ad590 and a few external resistors as shown in figure 19. from table ii simply choose the type of thermocouple and the appropriate average reference junction temperature to select values for r comp and r z . the cjc voltage is developed across r comp as a result of the ad592 1 m a/k output and is added to the thermocouple loop voltage. the 50 w potentiometer is biased by r z to provide the correct zero adjustment range appropriate for the divider and also translates the kelvin scale of the ad592 to celsius. to calibrate the circuit, put the thermocouple in an ice bath (or use a thermocouple simulator set to 0) and adjust the potentiometer for a 4 ma loop current. the span of the circuit in c is determined by matching the signal amplifier input voltage range to its temperature equivalent figure 18. utilizing the auxiliary amplifier to drive a load cell, 12 ma 8 ma output
AD693 rev. a C11C table ii. thermocouple applicationcold junction compensation 30 mv 60 mv ambient temp temp polarity material type temp rcomp rz range range + iron j 25 51.7 w 301k 546 c 1035 c C constantan 75 53.6 w 294k + nickel-chrome 25 40.2 w 392k 721 c _ nickel-aluminum k 75 42.2 w 374k + nickel-chrome 25 60.4 w 261k e 413 c 787 c C copper-nickel 75 64.9 w 243k + copper 25 40.2 w 392k t use with gain >2 C copper-nickel 75 45.3 w 340k figure 19. thermocouple inputs with cold junction compensation table iii lists the expressions required to calculate the total error. the AD693 is tested with a 250 w load, a 24 v loop supply table iii. rti contributions to span and offset error rti contributions to offset error error source expression for rti error at zero i ze zero current error i ze /x s psrr power supply rejection ratio (|v loop C 24 v| + [|r l C 250 w | i z ]) psrr cmrr common-mode rejection ratio |v cm C 3.1 v| cmrr ios input offset current r s ios rti contributions to span error error source expression for rti error at full scale x se transconductance error v span x se x psrr transconductance psrr 1 |r l C 250 w | i s psrr x cmrr transconductance cmrr |v cm C 3.1 v| v span x cmrr x nl nonlinearity v span x nl i diff differential input current 2 rs i diff abbreviations i z zero current (usually 4 ma) i s output span (usually 16 ma) r s input source impedance r l load resistance v loop loop supply voltage v cm input common-mode voltage v span input span x s nominal transconductance in a/v 1 the 4C20 ma signal, flowing through the metering resistor, modulates the power supply voltage seen by the AD693. the change in voltage causes a power supply rejection error that varies with the output current, thus it appears as a span error. 2 the input bias current of the inverting input increases with input signal voltage. the differential input current, i diff , equals the inverting input current minus the noninverting input current; see figure 2. i diff , flowing into an input source impedance, will cause an input voltage error that var- ies with signal. if the change in differential input current with input signal is approximated as a linear function, then any error due to source impedance may be approximated as a span error. to calculate i diff , refer to figure 2 and find the value for i diff / + in corresponding to the full-scale input voltage for your application. multiply by + in max to get i dlff . multiply i diff by the source impedance to get the input voltage error at full scale. via a set of thermocouple tables referenced to c. for example, the output of a properly referenced type j thermocouple is 60 mv when the hot junction is at 1035 c. table ii lists the maximum measurement temperature for several thermocouple types using the preadjusted 30 mv and 60 mv input ranges. more convenient temperature ranges can be selected by deter- mining the full-scale input voltages via standard thermocouple tables and adjusting the AD693 span. for example, suppose only a 300 c span is to be measured with a type k thermo- couple. from a standard table, the thermocouple output is 12.207 mv; since 60 mv at the signal amplifier corresponds to a 16 ma span at the output a gain of 5, or more precisely 60 mv/ 12.207 mv = 4.915 will be needed. using a 12.207 mv span in the gain resistor formula given in adjusting input span yields a value of about 270 w as the minimum from p1 to 6.2 v. adding a 50 w potentiometer will allow ample adjustment range. with the connection illustrated, the AD693 will give a full-scale indication with an open thermocouple. error budget analysis loop-powered operation specifications refer to parameters tested with the AD693 operating as a loop-powered transmitter. the specifications are valid for the preset spans of 30 mv, 60 mv and those spans in between. the section, components of error, refers to parameters tested on the individual functional blocks, (signal amplifier, v/i converter, voltage reference, and auxiliary amplifier). these can be used to get an indication of device performance when the AD693 is used in local power mode or when it is adjusted to spans of less than 30 mv.
AD693 rev. a C12C c1050aC9C10/87 printed in u.s.a. error it is necessary to add an error of only (5 C 2) v os to the error budget. note that span error may by reduced to zero with the span trim, leaving only the offset and nonlinearity of the AD693. example i the AD693 is configured as a 4-20ma loop powered transmitter with a 60 mv fs input. the inputs are driven by a differential voltage at 2 v common mode with a 300 w balanced source resistance. a 24 v loop supply is used with a 500 w metering resistance. (see table iv below.) trimming the offset and span for your application will remove all span and offset errors except the nonlinearity of the AD693. table iv. example 1 offset errors i z already included in the tue spec . 0.0 m v psrr psrr = 5.6 m v/v; ( | 24 v C 24 v| + [ | 500 w C 250 w 4 ma ] ) 5.6 m v/v =5.6 m v v loop = 24 v r l = 500 w i z = 4 ma cmrr cmrr = 30 m v/v; |2 v C3.1 v| 30 m v/v = 33.0 m v v cm = 2 v ios ios = 3 na, r s = 300 w ; 300 w 3 na = 0.9 m v total additional error at 4 ma 39.5 m v as % of full scale; (39.5 m v 0.2666 a/v)/20 ma 100% = 0.053 % of fs span errors x se already included in the tue spec 0.0 m v x psrr psrr = 5.6 m v/v; (|500 w C 250 w | 16 ma) 5.6 m v/v = 22.4 m v r l = 500 w , i s = 16 ma x cmrr x cmrr = 0.06%/v; |2 v C 3. 1 v| 60 mv 0.06%/v = 39.6 m v v cm = 2 v, v span = 60 mv i diff v span = +60 mv; 300 w 2 20 na 12.0 m v i diff / + in = 2 from figure 2) x nl already included in the tue 0.0 m v total additional span error at full scale 74.0 m v total additional error at full scale; e offset + e span = 39.5 m v + 74.0 m v = 113.5 m v as % of full scale; (113.5 m v 0.2666a v)/20 ma 100% = 0.151% of fs new total unadjusted error @ fs; e tue + e additional = 0.5% +0.151% = 0.651% of fs and an input common-mode voltage of 3.1 v. the expressions below calculate errors due to deviations from these nominal conditions. the total error at zero consists only of offset errors. the total error at full scale consists of the offset errors plus the span errors. adding the above errors in this manner may result in an error as large as 0.8% of full scale, however, as a rule, the AD693 performs better as the span and offset errors do not tend to add worst case. the specification total unadjusted error, (tue), reflects this and gives the maximum error as a % of full scale for any point in the transfer function when the device is operated in one of its preset spans, with no external trims. the tue is less than the error you would get by adding the span and offset errors worst case. thus, an alternative way of calculating the total error is to start with the tue and add to it those errors that result from operation of the AD693 with a load resistance, loop supply voltage, or common-mode input voltage different than specified. (see example 1 below.) error budget for spans less than 30 mv an accommodation must be made to include the input voltage offset of the signal amplifier when the span is adjusted to less than 30 mv. the tue and the zero current error include the input offset voltage contribution of the signal amplifier in a gain of 2. as the input offset voltage is multiplied by the gain of the signal amplifier, one must include the additional error when the signal amplifier is set to gains greater than 2. for example, the 300k span thermocouple application discussed previously requires a 12.207 mv input span; the signal amplifier must be adjusted to a gain of approximately 5. the loop trans- conductance is now 1.333 a/v, (5 0.2666 a/v). calculate the total error by substituting the new values for the transconductance and span into the equations in table iii as was done in example i. the error contribution due to v os is 5 v os , however, since 2 v os is already included in the tue and the zero current e-20a 20-terminal leadless chip carrier d-20 20-lead side brazed ceramic dip q-20 20-lead cerdip outline dimensions dimensions shown in inches and (mm).

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